XCENA Details MX1 Architecture Integrating Memory Expansion and Near-Memory Computing at Hot Chips 2026

Single CXL Type 3 device combines up to 2 TB of DDR5, SSD-backed capacity and 1,000+ RISC-V cores

Benchmark tests show up to 4.7x the throughput and 18.7x the energy efficiency of host CPU processing over CXL on selected data-analytics kernels

XCENA, a semiconductor company developing memory-centric computing solutions for AI infrastructure, today presented the architecture and measured performance of MX1, its computational CXL memory architecture, during the Hot Chips 2026 Memory session. Presented by Harry Kim, Chief Product Officer of XCENA, the session examined how MX1 combines large-scale memory expansion, SSD-backed capacity and programmable near-memory computing in a single CXL Type 3 device to address the growing memory constraints of AI infrastructure.

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The MX1 presentation was selected through the Hot Chips program committee's technical review process.

As AI models continue to grow, system performance is increasingly constrained by memory capacity, data movement and the economics of high-bandwidth memory scaling rather than compute alone. MX1 is designed to complement CPUs, GPUs and AI accelerators by expanding memory capacity and offloading selected memory-bound operations—including vector search, KV-cache retrieval and data preprocessing—so host processors can focus on compute-intensive inference.

MX1 integrates three architectural capabilities within a single CXL Type 3 device:

• Memory expansion — Up to 2 TB of DDR5 across four memory channels connected through CXL 3.2 over PCIe 6.0.
• SSD-backed capacity — XCENA InfiniteMemory® exposes SSD capacity through a byte-addressable CXL memory interface while transparently caching frequently accessed 64 KB pages in DRAM.
• Near-memory computing — 1,000+ custom RISC-V cores organized into Memory Acceleration Units execute highly parallel, memory-intensive workloads close to the data. Integrated vector engines provide approximately 3 TFLOPS of FP32/FP16 dot-product throughput for workloads including vector search and KV-cache scoring.

“Hot Chips is where the industry evaluates new computing architectures based on technical merit,” said Harry Kim, Chief Product Officer of XCENA. “Our presentation shares the architectural design, software model and measured performance of MX1, demonstrating how computational CXL memory can help address the growing capacity and data-movement challenges facing AI infrastructure.”

Measured performance on representative data-processing workloads

XCENA evaluated MX1 across six representative data-processing kernels commonly found in analytics and AI pipelines: compression, decompression, Parquet decoding, less-than filtering, LIKE filtering and aggregation.

Compared with a host CPU processing data over CXL, a single MX1 delivered up to 4.7x higher throughput and 18.7x greater energy efficiency. Compared with the same host CPU processing data from local DDR5 memory, MX1 delivered up to 2.0x higher throughput and 6.2x greater energy efficiency.¹

“These results demonstrate the value of executing highly parallel, memory-bound workloads closer to where the data resides,” Kim said. “MX1 is designed to complement the host processor by reducing unnecessary data movement, allowing CPU resources to remain focused on operating system services, orchestration and general-purpose computation.”

Software model and availability

Developers program MX1 using standard C/C++ or Rust through XCENA’s LLVM-based software toolchain. The PXL runtime schedules and synchronizes workloads across the device’s RISC-V processing cores while providing a shared virtual address space that simplifies memory management for complex data structures and multi-application execution.

At the framework level, XCENA’s XFLARE analytics library integrates with SQL engines and FAISS-based vector search. The software stack is also being extended to support widely adopted AI and data frameworks, including Apache Arrow, PyTorch and vector databases, with additional SDK integrations planned over time. SDK information is available at xcena.com/sdk.

XCENA plans to begin mass production by the end of 2026, with initial customer revenue targeted for 2027.

About XCENA

XCENA is a memory-centric AI computing company redefining the role of memory in AI infrastructure. Built on the open Compute Express Link (CXL) standard, XCENA develops products that enable memory to be expanded and utilized more efficiently, helping customers improve AI infrastructure performance while reducing latency, power consumption, and total cost of ownership (TCO).

Founded by semiconductor veterans from Samsung Electronics and SK hynix, XCENA combines expertise in semiconductor design with a full-stack software development kit (SDK) to help hyperscalers, cloud providers, and enterprises deploy and optimize AI infrastructure at scale. Headquartered in Seongnam, South Korea, with a U.S. office in Sunnyvale, California, XCENA has raised US$185 million to date, including a US$135 million Series B financing. Learn more at www.xcena.com.

¹ Measured across six data-analytics kernels (compression, decompression, Parquet decoding, less-than filter, LIKE filter and aggregation) comparing a single MX1 with a host CPU pinned to a single NUMA node in three configurations: host with local DDR5, host processing data over CXL and MX1 offload. Throughput = input size ÷ elapsed time. Energy efficiency = throughput ÷ active power above system idle. Results vary by workload and configuration. Full methodology will be included in the Hot Chips 2026 presentation materials.

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